369 lines
8.9 KiB
C++
369 lines
8.9 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#define _PC_ // disables MIPS opcode macros.
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#include "R3000A.h"
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#include "Common.h"
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#include "Sif.h"
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#include "IopHw.h"
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_sif sif1;
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static bool done = false;
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static bool sif1_dma_stall = false;
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static __fi void Sif1Init()
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{
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SIF_LOG("SIF1 DMA start...");
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done = false;
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sif1.ee.cycles = 0;
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sif1.iop.cycles = 0;
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}
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// Write from the EE to Fifo.
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static __fi bool WriteEEtoFifo()
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{
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// There's some data ready to transfer into the fifo..
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SIF_LOG("Sif 1: Write EE to Fifo");
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const int writeSize = std::min((s32)sif1ch.qwc, sif1.fifo.sif_free() >> 2);
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tDMA_TAG *ptag;
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ptag = sif1ch.getAddr(sif1ch.madr, DMAC_SIF1, false);
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if (ptag == NULL)
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{
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DevCon.Warning("Write EE to Fifo: ptag == NULL");
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return false;
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}
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sif1.fifo.write((u32*)ptag, writeSize << 2);
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sif1ch.madr += writeSize << 4;
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hwDmacSrcTadrInc(sif1ch);
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sif1.ee.cycles += writeSize; // fixme : BIAS is factored in above
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sif1ch.qwc -= writeSize;
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return true;
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}
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// Read from the fifo and write to IOP
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static __fi bool WriteFifoToIOP()
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{
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// If we're reading something, continue to do so.
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SIF_LOG("Sif1: Write Fifo to IOP");
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const int readSize = std::min(sif1.iop.counter, sif1.fifo.size);
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SIF_LOG("Sif 1 IOP doing transfer %04X to %08X", readSize, HW_DMA10_MADR);
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sif1.fifo.read((u32*)iopPhysMem(hw_dma10.madr), readSize);
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psxCpu->Clear(hw_dma10.madr, readSize);
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hw_dma10.madr += readSize << 2;
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sif1.iop.cycles += readSize >> 2; // fixme: should be >> 4
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sif1.iop.counter -= readSize;
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return true;
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}
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// Get a tag and process it.
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static __fi bool ProcessEETag()
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{
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// Chain mode
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tDMA_TAG *ptag;
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SIF_LOG("Sif1: ProcessEETag");
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// Process DMA tag at sif1ch.tadr
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ptag = sif1ch.DMAtransfer(sif1ch.tadr, DMAC_SIF1);
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if (ptag == NULL)
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{
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Console.WriteLn("Sif1 ProcessEETag: ptag = NULL");
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return false;
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}
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if (sif1ch.chcr.TTE)
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{
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Console.WriteLn("SIF1 TTE");
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sif1.fifo.write((u32*)ptag + 2, 2);
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}
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SIF_LOG("%s", ptag->tag_to_str().c_str());
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sif1ch.madr = ptag[1]._u32;
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sif1.ee.end = hwDmacSrcChain(sif1ch, ptag->ID);
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if (sif1ch.chcr.TIE && ptag->IRQ)
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{
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//Console.WriteLn("SIF1 TIE");
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sif1.ee.end = true;
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}
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return true;
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}
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// Write fifo to data, and put it in IOP.
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static __fi bool SIFIOPReadTag()
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{
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// Read a tag.
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sif1.fifo.read((u32*)&sif1.iop.data, 4);
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//sif1words = (sif1words + 3) & 0xfffffffc; // Round up to nearest 4.
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SIF_LOG("SIF 1 IOP: dest chain tag madr:%08X wc:%04X id:%X irq:%d",
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sif1data & 0xffffff, sif1words, sif1tag.ID, sif1tag.IRQ);
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// Only use the first 24 bits.
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hw_dma10.madr = sif1data & 0xffffff;
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if (sif1words > 0xFFFFC) DevCon.Warning("SIF1 Overrun %x", sif1words);
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//Maximum transfer amount 1mb-16 also masking out top part which is a "Mode" cache stuff, we don't care :)
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sif1.iop.counter = sif1words & 0xFFFFC;
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if (sif1tag.IRQ || (sif1tag.ID & 4)) sif1.iop.end = true;
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return true;
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}
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// Stop processing EE, and signal an interrupt.
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static __fi void EndEE()
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{
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sif1.ee.end = false;
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sif1.ee.busy = false;
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SIF_LOG("Sif 1: End EE");
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// Voodoocycles : Okami wants around 100 cycles when booting up
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// Other games reach like 50k cycles here, but the EE will long have given up by then and just retry.
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// (Cause of double interrupts on the EE)
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if (sif1.ee.cycles == 0)
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{
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SIF_LOG("SIF1 EE: cycles = 0");
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sif1.ee.cycles = 1;
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}
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CPU_SET_DMASTALL(DMAC_SIF1, false);
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CPU_INT(DMAC_SIF1, /*std::min((int)(*/sif1.ee.cycles*BIAS/*), 384)*/);
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}
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// Stop processing IOP, and signal an interrupt.
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static __fi void EndIOP()
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{
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sif1data = 0;
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sif1.iop.end = false;
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sif1.iop.busy = false;
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SIF_LOG("Sif 1: End IOP");
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//Fixme ( voodoocycles ):
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//The *24 are needed for ecco the dolphin (CDVD hangs) and silver surfer (Pad not detected)
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//Greater than *35 break rebooting when trying to play Tekken5 arcade history
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//Total cycles over 1024 makes SIF too slow to keep up the sound stream in so3...
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if (sif1.iop.cycles == 0)
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{
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DevCon.Warning("SIF1 IOP: cycles = 0");
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sif1.iop.cycles = 1;
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}
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// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords)
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PSX_INT(IopEvt_SIF1, /*std::min((*/sif1.iop.cycles/* * 26*//*), 1024)*/);
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}
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// Handle the EE transfer.
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static __fi void HandleEETransfer()
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{
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if(!sif1ch.chcr.STR)
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{
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//DevCon.Warning("Replacement for irq prevention hack EE SIF1");
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sif1.ee.end = false;
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sif1.ee.busy = false;
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return;
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}
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/*if (sif1ch.qwc == 0)
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if (sif1ch.chcr.MOD == NORMAL_MODE)
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if (!sif1.ee.end){
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DevCon.Warning("sif1 irq prevented CHCR %x QWC %x", sif1ch.chcr, sif1ch.qwc);
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done = true;
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return;
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}*/
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// If there's no more to transfer.
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if (sif1ch.qwc <= 0)
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{
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// If NORMAL mode or end of CHAIN then stop DMA.
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if ((sif1ch.chcr.MOD == NORMAL_MODE) || sif1.ee.end)
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{
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done = true;
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EndEE();
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}
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else
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{
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done = false;
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if (!ProcessEETag()) return;
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}
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}
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else
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{
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if (dmacRegs.ctrl.STD == STD_SIF1)
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{
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if ((sif1ch.chcr.MOD == NORMAL_MODE) || ((sif1ch.chcr.TAG >> 28) & 0x7) == TAG_REFS)
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{
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//DevCon.Warning("SIF1 Stall Control");
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const int writeSize = std::min((s32)sif1ch.qwc, sif1.fifo.sif_free() >> 2);
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if ((sif1ch.madr + (writeSize * 16)) > dmacRegs.stadr.ADDR)
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{
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hwDmacIrq(DMAC_STALL_SIS);
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sif1_dma_stall = true;
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CPU_SET_DMASTALL(DMAC_SIF1, true);
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return;
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}
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}
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//DevCon.Warning("SIF1 stall control Not Implemented"); // STD == fromSIF1
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}
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if (sif1.fifo.sif_free() > 0)
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{
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WriteEEtoFifo();
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}
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}
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}
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// Handle the IOP transfer.
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static __fi void HandleIOPTransfer()
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{
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if (sif1.iop.counter > 0)
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{
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if (sif1.fifo.size > 0)
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{
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WriteFifoToIOP();
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}
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}
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if (sif1.iop.counter <= 0)
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{
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if (sif1.iop.end)
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{
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done = true;
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EndIOP();
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}
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else if (sif1.fifo.size >= 4)
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{
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done = false;
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SIFIOPReadTag();
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}
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}
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}
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static __fi void Sif1End()
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{
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psHu32(SBUS_F240) &= ~0x40;
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psHu32(SBUS_F240) &= ~0x4000;
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DMA_LOG("SIF1 DMA End");
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}
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// Transfer EE to IOP, putting data in the fifo as an intermediate step.
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__fi void SIF1Dma()
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{
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int BusyCheck = 0;
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if (sif1_dma_stall)
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{
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const int writeSize = std::min((s32)sif1ch.qwc, sif1.fifo.sif_free() >> 2);
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if ((sif1ch.madr + (writeSize * 16)) > dmacRegs.stadr.ADDR)
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return;
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}
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sif1_dma_stall = false;
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Sif1Init();
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do
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{
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//I realise this is very hacky in a way but its an easy way of checking if both are doing something
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BusyCheck = 0;
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if (sif1.ee.busy && !sif1_dma_stall)
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{
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if(sif1.fifo.sif_free() > 0 || (sif1.ee.end && sif1ch.qwc == 0))
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{
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BusyCheck++;
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HandleEETransfer();
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}
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}
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if (sif1.iop.busy)
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{
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if(sif1.fifo.size >= 4 || (sif1.iop.end && sif1.iop.counter == 0))
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{
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BusyCheck++;
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HandleIOPTransfer();
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}
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}
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} while (/*!done &&*/ BusyCheck > 0);
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Sif1End();
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}
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__fi void sif1Interrupt()
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{
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HW_DMA10_CHCR &= ~0x01000000; //reset TR flag
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psxDmaInterrupt2(3);
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}
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__fi void EEsif1Interrupt()
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{
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hwDmacIrq(DMAC_SIF1);
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sif1ch.chcr.STR = false;
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}
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// Do almost exactly the same thing as psxDma10 in IopDma.cpp.
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// Main difference is this checks for iop, where psxDma10 checks for ee.
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__fi void dmaSIF1()
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{
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SIF_LOG("dmaSIF1 %s", sif1ch.cmqt_to_str().c_str());
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if (sif1.fifo.readPos != sif1.fifo.writePos)
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{
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SIF_LOG("warning, sif1.fifoReadPos != sif1.fifoWritePos");
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}
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psHu32(SBUS_F240) |= 0x4000;
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sif1.ee.busy = true;
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CPU_SET_DMASTALL(DMAC_SIF1, false);
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// Okay, this here is needed currently (r3644).
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// FFX battles in the thunder plains map die otherwise, Phantasy Star 4 as well
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// These 2 games could be made playable again by increasing the time the EE or the IOP run,
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// showing that this is very timing sensible.
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// Doing this DMA unfortunately brings back an old warning in Legend of Legaia though, but it still works.
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//Updated 23/08/2011: The hangs are caused by the EE suspending SIF1 DMA and restarting it when in the middle
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//of processing a "REFE" tag, so the hangs can be solved by forcing the ee.end to be false
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// (as it should always be at the beginning of a DMA). using "if iop is busy" flags breaks Tom Clancy Rainbow Six.
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// Legend of Legaia doesn't throw a warning either :)
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sif1.ee.end = false;
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if (sif1ch.chcr.MOD == CHAIN_MODE && sif1ch.qwc > 0)
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{
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if ((sif1ch.chcr.tag().ID == TAG_REFE) || (sif1ch.chcr.tag().ID == TAG_END) || (sif1ch.chcr.tag().IRQ && vif1ch.chcr.TIE))
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{
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sif1.ee.end = true;
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}
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}
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SIF1Dma();
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}
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