508 lines
11 KiB
C++
508 lines
11 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "common/AlignedMalloc.h"
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#include "R3000A.h"
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#include "Common.h"
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#include "ps2/pgif.h" // for PSX kernel TTY in iopMemWrite32
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#include "SPU2/spu2.h"
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#include "DEV9/DEV9.h"
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#include "IopHw.h"
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uptr *psxMemWLUT = NULL;
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const uptr *psxMemRLUT = NULL;
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IopVM_MemoryAllocMess* iopMem = NULL;
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alignas(__pagesize) u8 iopHw[Ps2MemSize::IopHardware];
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// --------------------------------------------------------------------------------------
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// iopMemoryReserve
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// --------------------------------------------------------------------------------------
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iopMemoryReserve::iopMemoryReserve()
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: _parent("IOP Main Memory (2mb)")
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{
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}
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iopMemoryReserve::~iopMemoryReserve()
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{
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Release();
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}
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void iopMemoryReserve::Assign(VirtualMemoryManagerPtr allocator)
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{
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psxMemWLUT = (uptr*)_aligned_malloc(0x2000 * sizeof(uptr) * 2, 16);
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if (!psxMemWLUT)
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pxFailRel("Failed to allocate IOP memory lookup table");
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memset((char*)psxMemWLUT, 0, 0x2000 * sizeof(uptr) * 2);
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psxMemRLUT = psxMemWLUT + 0x2000; //(uptr*)_aligned_malloc(0x10000 * sizeof(uptr),16);
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VtlbMemoryReserve::Assign(std::move(allocator), HostMemoryMap::IOPmemOffset, sizeof(*iopMem));
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iopMem = reinterpret_cast<IopVM_MemoryAllocMess*>(GetPtr());
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}
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void iopMemoryReserve::Release()
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{
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_parent::Release();
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safe_aligned_free(psxMemWLUT);
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psxMemRLUT = nullptr;
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iopMem = nullptr;
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}
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// Note! Resetting the IOP's memory state is dependent on having *all* psx memory allocated,
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// which is performed by MemInit and PsxMemInit()
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void iopMemoryReserve::Reset()
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{
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_parent::Reset();
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pxAssert( iopMem );
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DbgCon.WriteLn("IOP resetting main memory...");
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memset(psxMemWLUT, 0, 0x2000 * sizeof(uptr) * 2); // clears both allocations, RLUT and WLUT
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// Trick! We're accessing RLUT here through WLUT, since it's the non-const pointer.
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// So the ones with a 0x2000 prefixed are RLUT tables.
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// Map IOP main memory, which is Read/Write, and mirrored three times
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// at 0x0, 0x8000, and 0xa000:
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for (int i=0; i<0x0080; i++)
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{
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psxMemWLUT[i + 0x0000] = (uptr)&iopMem->Main[(i & 0x1f) << 16];
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// RLUTs, accessed through WLUT.
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psxMemWLUT[i + 0x2000] = (uptr)&iopMem->Main[(i & 0x1f) << 16];
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}
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// A few single-page allocations for things we store in special locations.
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psxMemWLUT[0x2000 + 0x1f00] = (uptr)iopMem->P;
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psxMemWLUT[0x2000 + 0x1f80] = (uptr)iopHw;
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//psxMemWLUT[0x1bf80] = (uptr)iopHw;
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psxMemWLUT[0x1f00] = (uptr)iopMem->P;
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psxMemWLUT[0x1f80] = (uptr)iopHw;
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//psxMemWLUT[0xbf80] = (uptr)iopHw;
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// Read-only memory areas, so don't map WLUT for these...
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for (int i = 0; i < 0x0040; i++)
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{
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psxMemWLUT[i + 0x2000 + 0x1fc0] = (uptr)&eeMem->ROM[i << 16];
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}
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for (int i = 0; i < 0x0040; i++)
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{
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psxMemWLUT[i + 0x2000 + 0x1e00] = (uptr)&eeMem->ROM1[i << 16];
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}
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for (int i = 0; i < 0x0008; i++)
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{
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psxMemWLUT[i + 0x2000 + 0x1e40] = (uptr)&eeMem->ROM2[i << 16];
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}
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// sif!! (which is read only? (air))
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psxMemWLUT[0x2000 + 0x1d00] = (uptr)iopMem->Sif;
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//psxMemWLUT[0x1bd00] = (uptr)iopMem->Sif;
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// this one looks like an old hack for some special write-only memory area,
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// but leaving it in for reference (air)
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//for (i=0; i<0x0008; i++) psxMemWLUT[i + 0xbfc0] = (uptr)&psR[i << 16];
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}
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u8 iopMemRead8(u32 mem)
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{
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mem &= 0x1fffffff;
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u32 t = mem >> 16;
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if (t == 0x1f80)
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{
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switch( mem & 0xf000 )
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{
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case 0x1000: return IopMemory::iopHwRead8_Page1(mem);
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case 0x3000: return IopMemory::iopHwRead8_Page3(mem);
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case 0x8000: return IopMemory::iopHwRead8_Page8(mem);
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default:
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return psxHu8(mem);
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}
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}
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else if (t == 0x1f40)
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{
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return psxHw4Read8(mem);
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}
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else
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{
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const u8* p = (const u8*)(psxMemRLUT[mem >> 16]);
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if (p != NULL)
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{
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return *(const u8 *)(p + (mem & 0xffff));
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}
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else
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{
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if (t == 0x1000)
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return DEV9read8(mem);
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PSXMEM_LOG("err lb %8.8lx", mem);
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return 0;
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}
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}
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}
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u16 iopMemRead16(u32 mem)
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{
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mem &= 0x1fffffff;
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u32 t = mem >> 16;
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if (t == 0x1f80)
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{
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switch( mem & 0xf000 )
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{
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case 0x1000: return IopMemory::iopHwRead16_Page1(mem);
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case 0x3000: return IopMemory::iopHwRead16_Page3(mem);
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case 0x8000: return IopMemory::iopHwRead16_Page8(mem);
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default:
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return psxHu16(mem);
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}
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}
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else
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{
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const u8* p = (const u8*)(psxMemRLUT[mem >> 16]);
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if (p != NULL)
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{
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if (t == 0x1d00)
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{
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u16 ret;
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switch(mem & 0xF0)
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{
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case 0x00:
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ret= psHu16(SBUS_F200);
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break;
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case 0x10:
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ret= psHu16(SBUS_F210);
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break;
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case 0x40:
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ret= psHu16(SBUS_F240) | 0x0002;
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break;
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case 0x60:
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ret = 0;
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break;
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default:
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ret = psxHu16(mem);
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break;
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}
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//SIF_LOG("Sif reg read %x value %x", mem, ret);
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return ret;
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}
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return *(const u16 *)(p + (mem & 0xffff));
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}
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else
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{
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if (t == 0x1F90)
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return SPU2read(mem);
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if (t == 0x1000)
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return DEV9read16(mem);
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PSXMEM_LOG("err lh %8.8lx", mem);
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return 0;
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}
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}
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}
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u32 iopMemRead32(u32 mem)
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{
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mem &= 0x1fffffff;
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u32 t = mem >> 16;
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if (t == 0x1f80)
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{
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switch( mem & 0xf000 )
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{
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case 0x1000: return IopMemory::iopHwRead32_Page1(mem);
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case 0x3000: return IopMemory::iopHwRead32_Page3(mem);
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case 0x8000: return IopMemory::iopHwRead32_Page8(mem);
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default:
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return psxHu32(mem);
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}
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} else
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{
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//see also Hw.c
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const u8* p = (const u8*)(psxMemRLUT[mem >> 16]);
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if (p != NULL)
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{
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if (t == 0x1d00)
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{
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u32 ret;
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switch(mem & 0x8F0)
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{
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case 0x00:
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ret= psHu32(SBUS_F200);
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break;
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case 0x10:
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ret= psHu32(SBUS_F210);
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break;
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case 0x20:
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ret= psHu32(SBUS_F220);
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break;
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case 0x30: // EE Side
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ret= psHu32(SBUS_F230);
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break;
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case 0x40:
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ret= psHu32(SBUS_F240) | 0xF0000002;
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break;
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case 0x60:
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ret = 0;
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break;
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default:
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ret = psxHu32(mem);
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break;
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}
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//SIF_LOG("Sif reg read %x value %x", mem, ret);
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return ret;
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}
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return *(const u32 *)(p + (mem & 0xffff));
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}
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else
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{
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if (t == 0x1000)
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return DEV9read32(mem);
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return 0;
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}
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}
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}
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void iopMemWrite8(u32 mem, u8 value)
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{
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mem &= 0x1fffffff;
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u32 t = mem >> 16;
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if (t == 0x1f80)
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{
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switch( mem & 0xf000 )
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{
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case 0x1000: IopMemory::iopHwWrite8_Page1(mem,value); break;
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case 0x3000: IopMemory::iopHwWrite8_Page3(mem,value); break;
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case 0x8000: IopMemory::iopHwWrite8_Page8(mem,value); break;
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default:
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psxHu8(mem) = value;
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break;
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}
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}
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else if (t == 0x1f40)
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{
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psxHw4Write8(mem, value);
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}
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else
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{
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u8* p = (u8 *)(psxMemWLUT[mem >> 16]);
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if (p != NULL && !(psxRegs.CP0.n.Status & 0x10000) )
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{
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*(u8 *)(p + (mem & 0xffff)) = value;
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psxCpu->Clear(mem&~3, 1);
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}
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else
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{
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if (t == 0x1d00)
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{
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Console.WriteLn("sw8 [0x%08X]=0x%08X", mem, value);
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psxSu8(mem) = value;
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return;
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}
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if (t == 0x1000)
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{
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DEV9write8(mem, value); return;
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}
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PSXMEM_LOG("err sb %8.8lx = %x", mem, value);
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}
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}
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}
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void iopMemWrite16(u32 mem, u16 value)
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{
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mem &= 0x1fffffff;
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u32 t = mem >> 16;
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if (t == 0x1f80)
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{
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switch( mem & 0xf000 )
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{
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case 0x1000: IopMemory::iopHwWrite16_Page1(mem,value); break;
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case 0x3000: IopMemory::iopHwWrite16_Page3(mem,value); break;
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case 0x8000: IopMemory::iopHwWrite16_Page8(mem,value); break;
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default:
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psxHu16(mem) = value;
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break;
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}
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} else
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{
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u8* p = (u8 *)(psxMemWLUT[mem >> 16]);
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if (p != NULL && !(psxRegs.CP0.n.Status & 0x10000) )
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{
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if( t==0x1D00 ) Console.WriteLn("sw16 [0x%08X]=0x%08X", mem, value);
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*(u16 *)(p + (mem & 0xffff)) = value;
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psxCpu->Clear(mem&~3, 1);
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}
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else
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{
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if (t == 0x1d00)
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{
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switch (mem & 0x8f0)
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{
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case 0x10:
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// write to ps2 mem
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psHu16(SBUS_F210) = value;
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return;
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case 0x40:
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{
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u32 temp = value & 0xF0;
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// write to ps2 mem
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if(value & 0x20 || value & 0x80)
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{
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psHu16(SBUS_F240) &= ~0xF000;
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psHu16(SBUS_F240) |= 0x2000;
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}
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if(psHu16(SBUS_F240) & temp)
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psHu16(SBUS_F240) &= ~temp;
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else
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psHu16(SBUS_F240) |= temp;
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return;
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}
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case 0x60:
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psHu32(SBUS_F260) = 0;
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return;
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}
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#if PSX_EXTRALOGS
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DevCon.Warning("IOP 16 Write to %x value %x", mem, value);
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#endif
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psxSu16(mem) = value; return;
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}
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if (t == 0x1F90) {
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SPU2write(mem, value); return;
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}
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if (t == 0x1000) {
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DEV9write16(mem, value); return;
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}
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PSXMEM_LOG("err sh %8.8lx = %x", mem, value);
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}
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}
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}
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void iopMemWrite32(u32 mem, u32 value)
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{
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mem &= 0x1fffffff;
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u32 t = mem >> 16;
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if (t == 0x1f80)
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{
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switch( mem & 0xf000 )
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{
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case 0x1000: IopMemory::iopHwWrite32_Page1(mem,value); break;
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case 0x3000: IopMemory::iopHwWrite32_Page3(mem,value); break;
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case 0x8000: IopMemory::iopHwWrite32_Page8(mem,value); break;
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default:
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psxHu32(mem) = value;
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break;
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}
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} else
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{
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//see also Hw.c
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u8* p = (u8 *)(psxMemWLUT[mem >> 16]);
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if( p != NULL && !(psxRegs.CP0.n.Status & 0x10000) )
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{
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*(u32 *)(p + (mem & 0xffff)) = value;
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psxCpu->Clear(mem&~3, 1);
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}
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else
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{
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if (t == 0x1d00)
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{
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MEM_LOG("iop Sif reg write %x value %x", mem, value);
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switch (mem & 0x8f0)
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{
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case 0x00: // EE write path (EE/IOP readable)
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return; // this is the IOP, so read-only (do nothing)
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case 0x10: // IOP write path (EE/IOP readable)
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psHu32(SBUS_F210) = value;
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return;
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case 0x20: // Bits cleared when written from IOP.
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psHu32(SBUS_F220) &= ~value;
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return;
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case 0x30: // bits set when written from IOP
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psHu32(SBUS_F230) |= value;
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return;
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case 0x40: // Control Register
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{
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u32 temp = value & 0xF0;
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if (value & 0x20 || value & 0x80)
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{
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psHu32(SBUS_F240) &= ~0xF000;
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psHu32(SBUS_F240) |= 0x2000;
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}
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if (psHu32(SBUS_F240) & temp)
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psHu32(SBUS_F240) &= ~temp;
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else
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psHu32(SBUS_F240) |= temp;
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return;
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}
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case 0x60:
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psHu32(SBUS_F260) = 0;
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return;
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}
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#if PSX_EXTRALOGS
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DevCon.Warning("IOP 32 Write to %x value %x", mem, value);
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#endif
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psxSu32(mem) = value;
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// wtf? why were we writing to the EE's sif space? Commenting this out doesn't
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// break any of my games, and should be more correct, but I guess we'll see. --air
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//*(u32*)(eeHw+0xf200+(mem&0xf0)) = value;
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return;
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}
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else if (t == 0x1000)
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{
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DEV9write32(mem, value); return;
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}
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}
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}
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}
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std::string iopMemReadString(u32 mem, int maxlen)
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{
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std::string ret;
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char c;
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while ((c = iopMemRead8(mem++)) && maxlen--)
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ret.push_back(c);
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return ret;
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}
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