569 lines
13 KiB
C++
569 lines
13 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "common/StringUtil.h"
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// Useful enums for some of the fields.
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enum pce_values
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{
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PCE_NOTHING = 0,
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PCE_RESERVED,
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PCE_DISABLED,
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PCE_ENABLED
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};
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enum tag_id
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{
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TAG_CNTS = 0,
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TAG_REFE = 0, // Transfer Packet According to ADDR field, clear STR, and end
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TAG_CNT, // Transfer QWC following the tag.
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TAG_NEXT, // Transfer QWC following tag. TADR = ADDR
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TAG_REF, // Transfer QWC from ADDR field
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TAG_REFS, // Transfer QWC from ADDR field (Stall Control)
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TAG_CALL, // Transfer QWC following the tag, save succeeding tag
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TAG_RET, // Transfer QWC following the tag, load next tag
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TAG_END // Transfer QWC following the tag
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};
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enum mfd_type
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{
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NO_MFD = 0,
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MFD_RESERVED,
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MFD_VIF1,
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MFD_GIF
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};
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enum sts_type
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{
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NO_STS = 0,
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STS_SIF0,
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STS_fromSPR,
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STS_fromIPU
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};
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enum std_type
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{
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NO_STD = 0,
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STD_VIF1,
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STD_GIF,
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STD_SIF1
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};
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enum LogicalTransferMode
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{
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NORMAL_MODE = 0,
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CHAIN_MODE,
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INTERLEAVE_MODE,
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UNDEFINED_MODE
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};
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//
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// --- DMA ---
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//
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// Doing double duty as both the top 32 bits *and* the lower 32 bits of a chain tag.
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// Theoretically should probably both be in a u64 together, but with the way the
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// code is layed out, this is easier for the moment.
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union tDMA_TAG {
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struct {
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u32 QWC : 16;
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u32 _reserved2 : 10;
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u32 PCE : 2;
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u32 ID : 3;
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u32 IRQ : 1;
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};
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struct {
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u32 ADDR : 31;
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u32 SPR : 1;
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};
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u32 _u32;
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tDMA_TAG() {}
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tDMA_TAG(u32 val) { _u32 = val; }
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u16 upper() const { return (_u32 >> 16); }
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u16 lower() const { return (u16)_u32; }
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std::string tag_to_str() const
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{
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switch(ID)
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{
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case TAG_REFE: return StringUtil::StdStringFromFormat("REFE %08X", _u32);
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case TAG_CNT: return "CNT";
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case TAG_NEXT: return StringUtil::StdStringFromFormat("NEXT %08X", _u32);
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case TAG_REF: return StringUtil::StdStringFromFormat("REF %08X", _u32);
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case TAG_REFS: return StringUtil::StdStringFromFormat("REFS %08X", _u32);
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case TAG_CALL: return "CALL";
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case TAG_RET: return "RET";
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case TAG_END: return "END";
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default: return "????";
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}
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}
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void reset() { _u32 = 0; }
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};
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#define DMA_TAG(value) ((tDMA_TAG)(value))
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union tDMA_CHCR {
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struct {
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u32 DIR : 1; // Direction: 0 - to memory, 1 - from memory. VIF1 & SIF2 only.
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u32 _reserved1 : 1;
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u32 MOD : 2; // Logical transfer mode. Normal, Chain, or Interleave (see LogicalTransferMode enum)
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u32 ASP : 2; // ASP1 & ASP2; Address stack pointer. 0, 1, or 2 addresses.
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u32 TTE : 1; // Tag Transfer Enable. 0 - Disable / 1 - Enable.
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u32 TIE : 1; // Tag Interrupt Enable. 0 - Disable / 1 - Enable.
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u32 STR : 1; // Start. 0 while stopping DMA, 1 while it's running.
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u32 _reserved2 : 7;
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u32 TAG : 16; // Maintains upper 16 bits of the most recently read DMAtag.
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};
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u32 _u32;
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tDMA_CHCR( u32 val) { _u32 = val; }
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bool test(u32 flags) const { return !!(_u32 & flags); }
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void set(u32 value) { _u32 = value; }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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u16 upper() const { return (_u32 >> 16); }
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u16 lower() const { return (u16)_u32; }
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std::string desc() const { return StringUtil::StdStringFromFormat("Chcr: 0x%x", _u32); }
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tDMA_TAG tag() { return (tDMA_TAG)_u32; }
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};
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#define CHCR(value) ((tDMA_CHCR)(value))
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union tDMA_SADR {
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struct {
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u32 ADDR : 14;
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u32 reserved2 : 18;
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};
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u32 _u32;
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tDMA_SADR(u32 val) { _u32 = val; }
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void reset() { _u32 = 0; }
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std::string desc() const { return StringUtil::StdStringFromFormat("Sadr: 0x%x", _u32); }
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tDMA_TAG tag() const { return (tDMA_TAG)_u32; }
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};
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union tDMA_QWC {
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struct {
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u32 QWC;
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};
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u32 _u32;
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tDMA_QWC(u32 val) { _u32 = val; }
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void reset() { _u32 = 0; }
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std::string desc() const { return StringUtil::StdStringFromFormat("QWC: 0x%04x", QWC); }
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tDMA_TAG tag() const { return (tDMA_TAG)_u32; }
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};
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struct DMACh {
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tDMA_CHCR chcr;
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u32 _null0[3];
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u32 madr;
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u32 _null1[3];
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u32 qwc;
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u32 _null2[3];
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u32 tadr;
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u32 _null3[3];
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u32 asr0;
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u32 _null4[3];
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u32 asr1;
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u32 _null5[11];
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u32 sadr;
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void chcrTransfer(tDMA_TAG* ptag)
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{
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chcr.TAG = ptag[0].upper();
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}
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void qwcTransfer(tDMA_TAG* ptag)
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{
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qwc = ptag[0].QWC;
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}
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bool transfer(const char *s, tDMA_TAG* ptag);
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void unsafeTransfer(tDMA_TAG* ptag);
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tDMA_TAG *getAddr(u32 addr, u32 num, bool write);
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tDMA_TAG *DMAtransfer(u32 addr, u32 num);
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tDMA_TAG dma_tag();
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std::string cmq_to_str() const;
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std::string cmqt_to_str() const;
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};
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enum INTCIrqs
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{
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INTC_GS = 0,
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INTC_SBUS,
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INTC_VBLANK_S,
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INTC_VBLANK_E,
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INTC_VIF0,
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INTC_VIF1,
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INTC_VU0,
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INTC_VU1,
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INTC_IPU,
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INTC_TIM0,
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INTC_TIM1,
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INTC_TIM2,
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INTC_TIM3,
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INTC_SFIFO,
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INTVU0_WD
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};
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enum dmac_conditions
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{
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DMAC_STAT_SIS = (1<<13), // stall condition
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DMAC_STAT_MEIS = (1<<14), // mfifo empty
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DMAC_STAT_BEIS = (1<<15), // bus error
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DMAC_STAT_SIM = (1<<29), // stall mask
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DMAC_STAT_MEIM = (1<<30) // mfifo mask
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};
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//DMA interrupts & masks
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enum DMAInter
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{
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BEISintr = 0x00008000,
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VIF0intr = 0x00010001,
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VIF1intr = 0x00020002,
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GIFintr = 0x00040004,
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IPU0intr = 0x00080008,
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IPU1intr = 0x00100010,
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SIF0intr = 0x00200020,
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SIF1intr = 0x00400040,
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SIF2intr = 0x00800080,
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SPR0intr = 0x01000100,
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SPR1intr = 0x02000200,
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SISintr = 0x20002000,
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MEISintr = 0x40004000
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};
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union tDMAC_QUEUE
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{
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struct
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{
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u16 VIF0 : 1;
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u16 VIF1 : 1;
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u16 GIF : 1;
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u16 IPU0 : 1;
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u16 IPU1 : 1;
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u16 SIF0 : 1;
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u16 SIF1 : 1;
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u16 SIF2 : 1;
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u16 SPR0 : 1;
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u16 SPR1 : 1;
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u16 SIS : 1;
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u16 MEIS : 1;
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u16 BEIS : 1;
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};
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u16 _u16;
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tDMAC_QUEUE(u16 val) { _u16 = val; }
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void reset() { _u16 = 0; }
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bool empty() const { return (_u16 == 0); }
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};
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static __fi const char* ChcrName(u32 addr)
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{
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switch (addr)
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{
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case D0_CHCR: return "Vif 0";
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case D1_CHCR: return "Vif 1";
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case D2_CHCR: return "GIF";
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case D3_CHCR: return "Ipu 0";
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case D4_CHCR: return "Ipu 1";
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case D5_CHCR: return "Sif 0";
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case D6_CHCR: return "Sif 1";
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case D7_CHCR: return "Sif 2";
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case D8_CHCR: return "SPR 0";
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case D9_CHCR: return "SPR 1";
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default: return "???";
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}
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}
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// Believe it or not, making this const can generate compiler warnings in gcc.
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static __fi int ChannelNumber(u32 addr)
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{
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switch (addr)
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{
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case D0_CHCR: return 0;
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case D1_CHCR: return 1;
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case D2_CHCR: return 2;
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case D3_CHCR: return 3;
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case D4_CHCR: return 4;
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case D5_CHCR: return 5;
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case D6_CHCR: return 6;
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case D7_CHCR: return 7;
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case D8_CHCR: return 8;
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case D9_CHCR: return 9;
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default:
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{
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pxFailDev("Invalid DMA channel number");
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return 51; // some value
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}
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}
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}
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union tDMAC_CTRL {
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struct {
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u32 DMAE : 1; // 0/1 - disables/enables all DMAs
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u32 RELE : 1; // 0/1 - cycle stealing off/on
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u32 MFD : 2; // Memory FIFO drain channel (mfd_type)
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u32 STS : 2; // Stall Control source channel (sts type)
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u32 STD : 2; // Stall Control drain channel (std_type)
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u32 RCYC : 3; // Release cycle (8/16/32/64/128/256)
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u32 _reserved1 : 21;
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};
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u32 _u32;
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tDMAC_CTRL(u32 val) { _u32 = val; }
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bool test(u32 flags) const { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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std::string desc() const { return StringUtil::StdStringFromFormat("Ctrl: 0x%x", _u32); }
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};
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union tDMAC_STAT {
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struct {
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u32 CIS : 10;
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u32 _reserved1 : 3;
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u32 SIS : 1;
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u32 MEIS : 1;
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u32 BEIS : 1;
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u32 CIM : 10;
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u32 _reserved2 : 3;
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u32 SIM : 1;
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u32 MEIM : 1;
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u32 _reserved3 : 1;
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};
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u32 _u32;
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u16 _u16[2];
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tDMAC_STAT(u32 val) { _u32 = val; }
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bool test(u32 flags) const { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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std::string desc() const { return StringUtil::StdStringFromFormat("Stat: 0x%x", _u32); }
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bool TestForInterrupt() const
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{
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return ((_u16[0] & _u16[1]) != 0) || BEIS;
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}
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};
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union tDMAC_PCR {
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struct {
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u32 CPC : 10;
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u32 _reserved1 : 6;
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u32 CDE : 10;
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u32 _reserved2 : 5;
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u32 PCE : 1;
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};
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u32 _u32;
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tDMAC_PCR(u32 val) { _u32 = val; }
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bool test(u32 flags) const { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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std::string desc() const { return StringUtil::StdStringFromFormat("Pcr: 0x%x", _u32); }
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};
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union tDMAC_SQWC {
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struct {
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u32 SQWC : 8;
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u32 _reserved1 : 8;
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u32 TQWC : 8;
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u32 _reserved2 : 8;
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};
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u32 _u32;
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tDMAC_SQWC(u32 val) { _u32 = val; }
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bool test(u32 flags) const { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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std::string desc() const { return StringUtil::StdStringFromFormat("Sqwc: 0x%x", _u32); }
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};
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union tDMAC_RBSR {
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struct {
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u32 RMSK : 31;
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u32 _reserved1 : 1;
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};
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u32 _u32;
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tDMAC_RBSR(u32 val) { _u32 = val; }
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void reset() { _u32 = 0; }
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std::string desc() const { return StringUtil::StdStringFromFormat("Rbsr: 0x%x", _u32); }
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};
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union tDMAC_RBOR {
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struct {
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u32 ADDR : 31;
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u32 _reserved1 : 1;
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};
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u32 _u32;
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tDMAC_RBOR(u32 val) { _u32 = val; }
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void reset() { _u32 = 0; }
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std::string desc() const { return StringUtil::StdStringFromFormat("Rbor: 0x%x", _u32); }
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};
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// --------------------------------------------------------------------------------------
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// tDMAC_ADDR
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// --------------------------------------------------------------------------------------
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// This struct is used for several DMA address types, including some that do not have
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// effective SPR bit (the bit is ignored for all addresses that are not "allowed" to access
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// the scratchpad, including STADR, toSPR.MADR, fromSPR.MADR, etc.).
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//
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union tDMAC_ADDR
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{
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struct {
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u32 ADDR : 31; // Transfer memory address
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u32 SPR : 1; // Memory/SPR Address (only effective for MADR and TADR of non-SPR DMAs)
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};
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u32 _u32;
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tDMAC_ADDR() {}
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tDMAC_ADDR(u32 val) { _u32 = val; }
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void clear() { _u32 = 0; }
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void AssignADDR(uint addr)
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{
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ADDR = addr;
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if (SPR) ADDR &= (Ps2MemSize::Scratch-1);
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}
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void IncrementQWC(uint incval = 1)
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{
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ADDR += incval;
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if (SPR) ADDR &= (Ps2MemSize::Scratch-1);
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}
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std::string ToString(bool sprIsValid=true) const
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{
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return StringUtil::StdStringFromFormat((sprIsValid && SPR) ? "0x%04X(SPR)" : "0x%08X", ADDR);
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}
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};
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struct DMACregisters
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{
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tDMAC_CTRL ctrl;
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u32 _padding[3];
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tDMAC_STAT stat;
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u32 _padding1[3];
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tDMAC_PCR pcr;
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u32 _padding2[3];
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tDMAC_SQWC sqwc;
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u32 _padding3[3];
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tDMAC_RBSR rbsr;
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u32 _padding4[3];
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tDMAC_RBOR rbor;
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u32 _padding5[3];
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tDMAC_ADDR stadr;
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u32 _padding6[3];
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};
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|
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// Currently guesswork.
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union tINTC_STAT {
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struct {
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u32 interrupts : 10;
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u32 _placeholder : 22;
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};
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u32 _u32;
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tINTC_STAT(u32 val) { _u32 = val; }
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|
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bool test(u32 flags) const { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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std::string desc() const { return StringUtil::StdStringFromFormat("Stat: 0x%x", _u32); }
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};
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|
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union tINTC_MASK {
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struct {
|
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u32 int_mask : 10;
|
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u32 _placeholder:22;
|
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};
|
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u32 _u32;
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|
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tINTC_MASK(u32 val) { _u32 = val; }
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|
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bool test(u32 flags) const { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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|
void reset() { _u32 = 0; }
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|
std::string desc() const { return StringUtil::StdStringFromFormat("Mask: 0x%x", _u32); }
|
|
};
|
|
|
|
struct INTCregisters
|
|
{
|
|
tINTC_STAT stat;
|
|
u32 _padding1[3];
|
|
tINTC_MASK mask;
|
|
u32 _padding2[3];
|
|
};
|
|
|
|
#define intcRegs ((INTCregisters*)(eeHw+0xF000))
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|
|
|
static DMACregisters& dmacRegs = (DMACregisters&)eeHw[0xE000];
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|
|
|
// Various useful locations
|
|
static DMACh& vif0ch = (DMACh&)eeHw[0x8000];
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|
static DMACh& vif1ch = (DMACh&)eeHw[0x9000];
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|
static DMACh& gifch = (DMACh&)eeHw[0xA000];
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|
static DMACh& spr0ch = (DMACh&)eeHw[0xD000];
|
|
static DMACh& spr1ch = (DMACh&)eeHw[0xD400];
|
|
static DMACh& ipu0ch = (DMACh&)eeHw[0xb000];
|
|
static DMACh& ipu1ch = (DMACh&)eeHw[0xb400];
|
|
static DMACh& sif0ch = (DMACh&)eeHw[0xc000];
|
|
static DMACh& sif1ch = (DMACh&)eeHw[0xc400];
|
|
static DMACh& sif2dma = (DMACh&)eeHw[0xc800];
|
|
|
|
extern void throwBusError(const char *s);
|
|
extern void setDmacStat(u32 num);
|
|
extern tDMA_TAG *SPRdmaGetAddr(u32 addr, bool write);
|
|
extern tDMA_TAG *dmaGetAddr(u32 addr, bool write);
|
|
|
|
extern void hwIntcIrq(int n);
|
|
extern void hwDmacIrq(int n);
|
|
|
|
extern void FireMFIFOEmpty();
|
|
extern bool hwMFIFOWrite(u32 addr, const u128* data, uint size_qwc);
|
|
extern void hwMFIFOResume(u32 transferred);
|
|
extern void hwDmacSrcTadrInc(DMACh& dma);
|
|
extern bool hwDmacSrcChainWithStack(DMACh& dma, int id);
|
|
extern bool hwDmacSrcChain(DMACh& dma, int id);
|
|
|
|
template< uint page > u32 dmacRead32( u32 mem );
|
|
template< uint page > extern bool dmacWrite32( u32 mem, mem32_t& value );
|