Big update to the schematics

This commit is contained in:
Naoki Saito 2022-09-21 17:20:13 +01:00
parent 82fe49b615
commit aa20b9d242
212 changed files with 223943 additions and 10245 deletions

View File

Before

Width:  |  Height:  |  Size: 99 KiB

After

Width:  |  Height:  |  Size: 99 KiB

View File

Before

Width:  |  Height:  |  Size: 100 KiB

After

Width:  |  Height:  |  Size: 100 KiB

View File

Before

Width:  |  Height:  |  Size: 2.7 MiB

After

Width:  |  Height:  |  Size: 2.7 MiB

View File

Before

Width:  |  Height:  |  Size: 1.4 MiB

After

Width:  |  Height:  |  Size: 1.4 MiB

View File

Before

Width:  |  Height:  |  Size: 283 KiB

After

Width:  |  Height:  |  Size: 283 KiB

View File

Before

Width:  |  Height:  |  Size: 428 KiB

After

Width:  |  Height:  |  Size: 428 KiB

View File

Before

Width:  |  Height:  |  Size: 585 KiB

After

Width:  |  Height:  |  Size: 585 KiB

View File

@ -0,0 +1,343 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 2SD2352-Transistor_BJT
#
DEF 2SD2352-Transistor_BJT Q 0 0 Y N 1 F N
F0 "Q" 250 75 50 H V L CNN
F1 "2SD2352-Transistor_BJT" 250 0 50 H V L CNN
F2 "Package_TO_SOT_THT:TO-220-3_Horizontal_TabDown" 250 -75 50 H I L CIN
F3 "" 0 0 50 H I L CNN
$FPLIST
TO?3PB*
$ENDFPLIST
DRAW
P 2 0 1 0 0 0 30 0 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
C 50 0 111 0 1 10 N
X B 1 -200 0 200 R 50 50 1 1 I
X C 2 100 200 100 D 50 50 1 1 P
X E 3 100 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CP1_Small-Device
#
DEF CP1_Small-Device C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "CP1_Small-Device" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
P 2 0 1 12 -60 20 60 20 N
P 2 0 1 0 -50 60 -30 60 N
P 2 0 1 0 -40 50 -40 70 N
A 0 -140 125 614 1186 0 1 12 N 60 -30 -60 -30
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# D_Network08_Common_Anode-Diode
#
DEF D_Network08_Common_Anode-Diode DA 0 0 Y N 1 F N
F0 "DA" -500 0 50 V V C CNN
F1 "D_Network08_Common_Anode-Diode" 400 0 50 V V C CNN
F2 "Package_SIP:SIP9_Housing" 475 0 50 V I C CNN
F3 "" -100 -10 50 H I C CNN
$FPLIST
R?Array?SIP*
$ENDFPLIST
DRAW
S -450 -125 350 125 0 1 10 f
C -400 90 10 0 1 0 F
C -300 90 10 0 1 0 F
C -200 90 10 0 1 0 F
C -100 90 10 0 1 0 F
P 2 0 1 0 -400 -100 -400 -150 N
P 2 0 1 0 -400 -100 -400 -60 N
P 2 0 1 0 -400 -30 -400 -70 N
P 2 0 1 0 -400 -30 -400 -70 N
P 2 0 1 0 -400 20 -400 90 N
P 2 0 1 0 -400 20 -400 90 N
P 2 0 1 0 -370 -30 -430 -30 N
P 2 0 1 0 -370 -30 -430 -30 N
P 2 0 1 0 -370 20 -400 -30 N
P 2 0 1 0 -370 20 -400 -30 N
P 2 0 1 0 -300 -100 -300 -150 N
P 2 0 1 0 -300 -100 -300 -60 N
P 2 0 1 0 -300 -30 -300 -70 N
P 2 0 1 0 -300 -30 -300 -70 N
P 2 0 1 0 -300 20 -300 90 N
P 2 0 1 0 -300 20 -300 90 N
P 2 0 1 0 -270 -30 -330 -30 N
P 2 0 1 0 -270 -30 -330 -30 N
P 2 0 1 0 -270 20 -300 -30 N
P 2 0 1 0 -270 20 -300 -30 N
P 2 0 1 0 -200 -100 -200 -150 N
P 2 0 1 0 -200 -100 -200 -70 N
P 2 0 1 0 -200 -30 -200 -70 N
P 2 0 1 0 -200 -30 -200 -70 N
P 2 0 1 0 -200 20 -200 90 N
P 2 0 1 0 -200 20 -200 90 N
P 2 0 1 0 -170 -30 -230 -30 N
P 2 0 1 0 -170 -30 -230 -30 N
P 2 0 1 0 -170 20 -200 -30 N
P 2 0 1 0 -170 20 -200 -30 N
P 2 0 1 0 -100 -100 -100 -150 N
P 2 0 1 0 -100 -100 -100 -70 N
P 2 0 1 0 -100 -30 -100 -70 N
P 2 0 1 0 -100 -30 -100 -70 N
P 2 0 1 0 -100 20 -100 90 N
P 2 0 1 0 -100 20 -100 90 N
P 2 0 1 0 -70 -30 -130 -30 N
P 2 0 1 0 -70 -30 -130 -30 N
P 2 0 1 0 -70 20 -100 -30 N
P 2 0 1 0 -70 20 -100 -30 N
P 2 0 1 0 0 -100 0 -150 N
P 2 0 1 0 0 -100 0 -70 N
P 2 0 1 0 0 -30 0 -70 N
P 2 0 1 0 0 -30 0 -70 N
P 2 0 1 0 0 20 0 90 N
P 2 0 1 0 0 20 0 90 N
P 2 0 1 0 30 -30 -30 -30 N
P 2 0 1 0 30 -30 -30 -30 N
P 2 0 1 0 30 20 0 -30 N
P 2 0 1 0 30 20 0 -30 N
P 2 0 1 0 100 -100 100 -150 N
P 2 0 1 0 100 -100 100 -70 N
P 2 0 1 0 100 -30 100 -70 N
P 2 0 1 0 100 -30 100 -70 N
P 2 0 1 0 100 20 100 90 N
P 2 0 1 0 100 20 100 90 N
P 2 0 1 0 130 -30 70 -30 N
P 2 0 1 0 130 -30 70 -30 N
P 2 0 1 0 130 20 100 -30 N
P 2 0 1 0 130 20 100 -30 N
P 2 0 1 0 200 -100 200 -150 N
P 2 0 1 0 200 -100 200 -70 N
P 2 0 1 0 200 -30 200 -70 N
P 2 0 1 0 200 -30 200 -70 N
P 2 0 1 0 200 20 200 90 N
P 2 0 1 0 200 20 200 90 N
P 2 0 1 0 230 -30 170 -30 N
P 2 0 1 0 230 -30 170 -30 N
P 2 0 1 0 230 20 200 -30 N
P 2 0 1 0 230 20 200 -30 N
P 2 0 1 0 300 -100 300 -150 N
P 2 0 1 0 300 -100 300 -70 N
P 2 0 1 0 300 -30 300 -70 N
P 2 0 1 0 300 -30 300 -70 N
P 2 0 1 0 300 20 300 90 N
P 2 0 1 0 300 20 300 90 N
P 2 0 1 0 330 -30 270 -30 N
P 2 0 1 0 330 -30 270 -30 N
P 2 0 1 0 330 20 300 -30 N
P 2 0 1 0 330 20 300 -30 N
P 3 0 1 0 -370 20 -430 20 -400 -30 N
P 3 0 1 0 -370 20 -430 20 -400 -30 N
P 3 0 1 0 -270 20 -330 20 -300 -30 N
P 3 0 1 0 -270 20 -330 20 -300 -30 N
P 3 0 1 0 -170 20 -230 20 -200 -30 N
P 3 0 1 0 -170 20 -230 20 -200 -30 N
P 3 0 1 0 -70 20 -130 20 -100 -30 N
P 3 0 1 0 -70 20 -130 20 -100 -30 N
P 3 0 1 0 30 20 -30 20 0 -30 N
P 3 0 1 0 30 20 -30 20 0 -30 N
P 3 0 1 0 130 20 70 20 100 -30 N
P 3 0 1 0 130 20 70 20 100 -30 N
P 3 0 1 0 230 20 170 20 200 -30 N
P 3 0 1 0 230 20 170 20 200 -30 N
P 3 0 1 0 330 20 270 20 300 -30 N
P 3 0 1 0 330 20 270 20 300 -30 N
P 4 0 1 0 -400 60 -400 90 -300 90 -300 60 N
P 4 0 1 0 -300 60 -300 90 -200 90 -200 60 N
P 4 0 1 0 -200 60 -200 90 -100 90 -100 60 N
P 4 0 1 0 -100 60 -100 90 0 90 0 60 N
P 4 0 1 0 0 60 0 90 100 90 100 60 N
P 4 0 1 0 100 60 100 90 200 90 200 60 N
P 4 0 1 0 200 60 200 90 300 90 300 60 N
C 0 90 10 0 1 0 F
C 100 90 10 0 1 0 F
C 200 90 10 0 1 0 F
X common 1 -400 200 100 D 50 50 1 1 P
X R1 2 -400 -200 50 U 50 50 1 1 P
X R2 3 -300 -200 50 U 50 50 1 1 P
X R3 4 -200 -200 50 U 50 50 1 1 P
X R4 5 -100 -200 50 U 50 50 1 1 P
X R5 6 0 -200 50 U 50 50 1 1 P
X R6 7 100 -200 50 U 50 50 1 1 P
X R7 8 200 -200 50 U 50 50 1 1 P
X R8 9 300 -200 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# D_Network08_Common_Cathode-Diode
#
DEF D_Network08_Common_Cathode-Diode DA 0 0 Y N 1 F N
F0 "DA" -500 0 50 V V C CNN
F1 "D_Network08_Common_Cathode-Diode" 400 0 50 V V C CNN
F2 "Package_SIP:SIP9_Housing" 475 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R?Array?SIP*
$ENDFPLIST
DRAW
S -450 -125 350 125 0 1 10 f
C -400 90 10 0 1 0 F
C -300 90 10 0 1 0 F
C -200 90 10 0 1 0 F
C -100 90 10 0 1 0 F
P 2 0 1 0 -430 -30 -400 20 N
P 2 0 1 0 -430 20 -370 20 N
P 2 0 1 0 -400 -100 -400 -150 N
P 2 0 1 0 -400 -30 -400 -100 N
P 2 0 1 0 -400 20 -400 60 N
P 2 0 1 0 -330 -30 -300 20 N
P 2 0 1 0 -330 20 -270 20 N
P 2 0 1 0 -300 -100 -300 -150 N
P 2 0 1 0 -300 -30 -300 -100 N
P 2 0 1 0 -300 20 -300 60 N
P 2 0 1 0 -230 -30 -200 20 N
P 2 0 1 0 -230 20 -170 20 N
P 2 0 1 0 -200 -100 -200 -150 N
P 2 0 1 0 -200 -30 -200 -100 N
P 2 0 1 0 -200 20 -200 60 N
P 2 0 1 0 -130 -30 -100 20 N
P 2 0 1 0 -130 20 -70 20 N
P 2 0 1 0 -100 -100 -100 -150 N
P 2 0 1 0 -100 -30 -100 -100 N
P 2 0 1 0 -100 20 -100 60 N
P 2 0 1 0 -30 -30 0 20 N
P 2 0 1 0 -30 20 30 20 N
P 2 0 1 0 0 -100 0 -150 N
P 2 0 1 0 0 -30 0 -100 N
P 2 0 1 0 0 20 0 60 N
P 2 0 1 0 70 -30 100 20 N
P 2 0 1 0 70 20 130 20 N
P 2 0 1 0 100 -100 100 -150 N
P 2 0 1 0 100 -30 100 -100 N
P 2 0 1 0 100 20 100 60 N
P 2 0 1 0 170 -30 200 20 N
P 2 0 1 0 170 20 230 20 N
P 2 0 1 0 200 -100 200 -150 N
P 2 0 1 0 200 -30 200 -100 N
P 2 0 1 0 200 20 200 60 N
P 2 0 1 0 270 -30 300 20 N
P 2 0 1 0 270 20 330 20 N
P 2 0 1 0 300 -100 300 -150 N
P 2 0 1 0 300 -30 300 -100 N
P 2 0 1 0 300 20 300 60 N
P 3 0 1 0 -430 -30 -370 -30 -400 20 N
P 3 0 1 0 -330 -30 -270 -30 -300 20 N
P 3 0 1 0 -230 -30 -170 -30 -200 20 N
P 3 0 1 0 -130 -30 -70 -30 -100 20 N
P 3 0 1 0 -30 -30 30 -30 0 20 N
P 3 0 1 0 70 -30 130 -30 100 20 N
P 3 0 1 0 170 -30 230 -30 200 20 N
P 3 0 1 0 270 -30 330 -30 300 20 N
P 4 0 1 0 -400 60 -400 90 -300 90 -300 60 N
P 4 0 1 0 -300 60 -300 90 -200 90 -200 60 N
P 4 0 1 0 -200 60 -200 90 -100 90 -100 60 N
P 4 0 1 0 -100 60 -100 90 0 90 0 60 N
P 4 0 1 0 0 60 0 90 100 90 100 60 N
P 4 0 1 0 100 60 100 90 200 90 200 60 N
P 4 0 1 0 200 60 200 90 300 90 300 60 N
C 0 90 10 0 1 0 F
C 100 90 10 0 1 0 F
C 200 90 10 0 1 0 F
X common 1 -400 200 100 D 50 50 1 1 P
X R1 2 -400 -200 50 U 50 50 1 1 P
X R2 3 -300 -200 50 U 50 50 1 1 P
X R3 4 -200 -200 50 U 50 50 1 1 P
X R4 5 -100 -200 50 U 50 50 1 1 P
X R5 6 0 -200 50 U 50 50 1 1 P
X R6 7 100 -200 50 U 50 50 1 1 P
X R7 8 200 -200 50 U 50 50 1 1 P
X R8 9 300 -200 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# EMI_Filter_LCL-Device
#
DEF EMI_Filter_LCL-Device FL 0 10 Y N 1 F N
F0 "FL" 0 275 50 H V C CNN
F1 "EMI_Filter_LCL-Device" 0 200 50 H V C CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
Filter*
Resonator*
$ENDFPLIST
DRAW
S -225 150 225 0 0 1 10 f
A -180 100 20 1 1799 0 1 0 N -160 100 -200 100
A -140 100 20 1 1799 0 1 0 N -120 100 -160 100
A -100 100 20 1 1799 0 1 0 N -80 100 -120 100
S -40 30 40 40 0 1 0 F
A -60 100 20 1 1799 0 1 0 N -40 100 -80 100
P 2 0 1 0 -40 100 40 100 N
P 2 0 1 0 0 30 0 0 N
P 2 0 1 0 0 100 0 70 N
C 0 100 10 0 1 0 F
S 40 60 -40 70 0 1 0 F
A 60 100 20 1 1799 0 1 0 N 80 100 40 100
A 100 100 20 1 1799 0 1 0 N 120 100 80 100
A 140 100 20 1 1799 0 1 0 N 160 100 120 100
A 180 100 20 1 1799 0 1 0 N 200 100 160 100
X 1 1 -300 100 100 R 50 50 1 1 P
X 2 2 0 -100 100 U 50 50 1 1 P
X 3 3 300 100 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Jumper_NC_Small-Device
#
DEF Jumper_NC_Small-Device JP 0 30 N N 1 F N
F0 "JP" 0 80 50 H V C CNN
F1 "Jumper_NC_Small-Device" 10 -60 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SolderJumper*Bridged*
Jumper*
TestPoint*2Pads*
TestPoint*Bridge*
$ENDFPLIST
DRAW
C -40 0 20 0 1 0 N
C 40 0 20 0 1 0 N
A 0 -10 57 450 1350 0 1 0 N 40 30 -40 30
X 1 1 -100 0 40 R 50 50 0 1 P
X 2 2 100 0 40 L 50 50 0 1 P
ENDDRAW
ENDDEF
#
# Jumper_NO_Small-Device
#
DEF Jumper_NO_Small-Device JP 0 30 N N 1 F N
F0 "JP" 0 80 50 H V C CNN
F1 "Jumper_NO_Small-Device" 10 -60 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SolderJumper*Open*
Jumper*
TestPoint*2Pads*
TestPoint*Bridge*
$ENDFPLIST
DRAW
C -40 0 20 0 1 0 N
C 40 0 20 0 1 0 N
X 1 1 -100 0 40 R 50 50 0 1 P
X 2 2 100 0 40 L 50 50 0 1 P
ENDDRAW
ENDDEF
#
#End Library

View File

@ -0,0 +1,75 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "GN845-PWB.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

View File

@ -0,0 +1,325 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "GN845-PWB.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"pin_symbol_size": 0.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"fa6bdd2a-9913-4167-ba9d-af1829b3da4a",
""
]
],
"text_variables": {}
}

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,3 @@
(sym_lib_table
(lib (name "GN845-PWB-rescue")(type "Legacy")(uri "${KIPRJMOD}/GN845-PWB-rescue.lib")(options "")(descr ""))
)

View File

Before

Width:  |  Height:  |  Size: 426 KiB

After

Width:  |  Height:  |  Size: 426 KiB

View File

@ -0,0 +1,37 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# EMI_Filter_LCL-Device
#
DEF EMI_Filter_LCL-Device FL 0 10 Y N 1 F N
F0 "FL" 0 275 50 H V C CNN
F1 "EMI_Filter_LCL-Device" 0 200 50 H V C CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
Filter*
Resonator*
$ENDFPLIST
DRAW
S -225 150 225 0 0 1 10 f
A -180 100 20 1 1799 0 1 0 N -160 100 -200 100
A -140 100 20 1 1799 0 1 0 N -120 100 -160 100
A -100 100 20 1 1799 0 1 0 N -80 100 -120 100
S -40 30 40 40 0 1 0 F
A -60 100 20 1 1799 0 1 0 N -40 100 -80 100
P 2 0 1 0 -40 100 40 100 N
P 2 0 1 0 0 30 0 0 N
P 2 0 1 0 0 100 0 70 N
C 0 100 10 0 1 0 F
S 40 60 -40 70 0 1 0 F
A 60 100 20 1 1799 0 1 0 N 80 100 40 100
A 100 100 20 1 1799 0 1 0 N 120 100 80 100
A 140 100 20 1 1799 0 1 0 N 160 100 120 100
A 180 100 20 1 1799 0 1 0 N 200 100 160 100
X 1 1 -300 100 100 R 50 50 1 1 P
X 2 2 0 -100 100 U 50 50 1 1 P
X 3 3 300 100 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

View File

@ -0,0 +1,75 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "GX700-PWB.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

View File

@ -0,0 +1,325 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "GX700-PWB.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"pin_symbol_size": 0.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"a135cf65-504a-4cf0-aa6e-c7f0f2982f6c",
""
]
],
"text_variables": {}
}

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,3 @@
(sym_lib_table
(lib (name "GX700-PWB-rescue")(type "Legacy")(uri "${KIPRJMOD}/GX700-PWB-rescue.lib")(options "")(descr ""))
)

View File

Before

Width:  |  Height:  |  Size: 338 KiB

After

Width:  |  Height:  |  Size: 338 KiB

View File

Before

Width:  |  Height:  |  Size: 297 KiB

After

Width:  |  Height:  |  Size: 297 KiB

View File

Before

Width:  |  Height:  |  Size: 293 KiB

After

Width:  |  Height:  |  Size: 293 KiB

View File

Before

Width:  |  Height:  |  Size: 60 KiB

After

Width:  |  Height:  |  Size: 60 KiB

View File

Before

Width:  |  Height:  |  Size: 1.2 MiB

After

Width:  |  Height:  |  Size: 1.2 MiB

View File

Before

Width:  |  Height:  |  Size: 1.3 MiB

After

Width:  |  Height:  |  Size: 1.3 MiB

View File

Before

Width:  |  Height:  |  Size: 1.3 MiB

After

Width:  |  Height:  |  Size: 1.3 MiB

View File

Before

Width:  |  Height:  |  Size: 1.2 MiB

After

Width:  |  Height:  |  Size: 1.2 MiB

View File

Before

Width:  |  Height:  |  Size: 413 KiB

After

Width:  |  Height:  |  Size: 413 KiB

View File

Before

Width:  |  Height:  |  Size: 183 KiB

After

Width:  |  Height:  |  Size: 183 KiB

View File

Before

Width:  |  Height:  |  Size: 182 KiB

After

Width:  |  Height:  |  Size: 182 KiB

View File

@ -0,0 +1,557 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 74xx_74LS139
#
DEF 74xx_74LS139 U 0 40 Y Y 3 L N
F0 "U" -300 350 50 H V C CNN
F1 "74xx_74LS139" -300 -350 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP?16*
$ENDFPLIST
DRAW
S -300 200 300 -300 1 1 10 f
S -300 200 300 -300 2 1 10 f
S -200 300 200 -300 3 1 10 f
X E 1 -500 -200 200 R 50 50 1 0 I I
X A0 2 -500 0 200 R 50 50 1 0 I
X A1 3 -500 100 200 R 50 50 1 0 I
X O0 4 500 100 200 L 50 50 1 0 O I
X O1 5 500 0 200 L 50 50 1 0 O I
X O2 6 500 -100 200 L 50 50 1 0 O I
X O3 7 500 -200 200 L 50 50 1 0 O I
X O2 10 500 -100 200 L 50 50 2 0 O I
X O1 11 500 0 200 L 50 50 2 0 O I
X O0 12 500 100 200 L 50 50 2 0 O I
X A1 13 -500 100 200 R 50 50 2 0 I
X A0 14 -500 0 200 R 50 50 2 0 I
X E 15 -500 -200 200 R 50 50 2 0 I I
X O3 9 500 -200 200 L 50 50 2 0 O I
X VCC 16 0 500 200 D 50 50 3 0 W
X GND 8 0 -500 200 U 50 50 3 0 W
ENDDRAW
ENDDEF
#
# Connector_Conn_01x06_Male
#
DEF Connector_Conn_01x06_Male J 0 40 Y N 1 F N
F0 "J" 0 300 50 H V C CNN
F1 "Connector_Conn_01x06_Male" 0 -400 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S 34 -295 0 -305 1 1 6 F
S 34 -195 0 -205 1 1 6 F
S 34 -95 0 -105 1 1 6 F
S 34 5 0 -5 1 1 6 F
S 34 105 0 95 1 1 6 F
S 34 205 0 195 1 1 6 F
P 2 1 1 6 50 -300 34 -300 N
P 2 1 1 6 50 -200 34 -200 N
P 2 1 1 6 50 -100 34 -100 N
P 2 1 1 6 50 0 34 0 N
P 2 1 1 6 50 100 34 100 N
P 2 1 1 6 50 200 34 200 N
X Pin_1 1 200 200 150 L 50 50 1 1 P
X Pin_2 2 200 100 150 L 50 50 1 1 P
X Pin_3 3 200 0 150 L 50 50 1 1 P
X Pin_4 4 200 -100 150 L 50 50 1 1 P
X Pin_5 5 200 -200 150 L 50 50 1 1 P
X Pin_6 6 200 -300 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Micro_SD_Card
#
DEF Connector_Micro_SD_Card J 0 40 Y Y 1 F N
F0 "J" -650 600 50 H V C CNN
F1 "Connector_Micro_SD_Card" 650 600 50 H V R CNN
F2 "" 1150 300 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
microSD*
$ENDFPLIST
DRAW
S -300 -375 -200 -425 0 1 0 F
S -300 -275 -200 -325 0 1 0 F
S -300 -175 -200 -225 0 1 0 F
S -300 -75 -200 -125 0 1 0 F
S -300 25 -200 -25 0 1 0 F
S -300 125 -200 75 0 1 0 F
S -300 225 -200 175 0 1 0 F
S -300 325 -200 275 0 1 0 F
P 6 0 1 10 650 500 650 550 -750 550 -750 -650 650 -650 650 -450 N
P 11 0 1 10 -350 -450 -350 350 -50 350 100 500 150 500 150 450 250 450 300 500 800 500 800 -450 -350 -450 f
X DAT2 1 -900 300 150 R 50 50 1 1 B
X DAT3/CD 2 -900 200 150 R 50 50 1 1 B
X CMD 3 -900 100 150 R 50 50 1 1 I
X VDD 4 -900 0 150 R 50 50 1 1 W
X CLK 5 -900 -100 150 R 50 50 1 1 I
X VSS 6 -900 -200 150 R 50 50 1 1 W
X DAT0 7 -900 -300 150 R 50 50 1 1 B
X DAT1 8 -900 -400 150 R 50 50 1 1 B
X SHIELD 9 800 -600 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_USB_A
#
DEF Connector_USB_A J 0 40 Y Y 1 F N
F0 "J" -200 450 50 H V L CNN
F1 "Connector_USB_A" -200 350 50 H V L CNN
F2 "" 150 -50 50 H I C CNN
F3 "" 150 -50 50 H I C CNN
$FPLIST
USB*
$ENDFPLIST
DRAW
C -150 85 25 0 1 10 F
C -25 135 15 0 1 10 F
S -200 -300 200 300 0 1 10 f
S -60 190 -170 210 0 1 0 F
S -50 180 -180 230 0 1 0 N
S -5 -300 5 -270 0 1 0 N
S 10 50 -20 20 0 1 10 F
S 200 -105 170 -95 0 1 0 N
S 200 -5 170 5 0 1 0 N
S 200 195 170 205 0 1 0 N
P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N
P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N
P 4 0 1 10 25 110 25 60 75 85 25 110 F
P 2 1 1 10 -75 85 25 85 N
X VBUS 1 300 200 100 L 50 50 1 1 W
X D- 2 300 -100 100 L 50 50 1 1 B
X D+ 3 300 0 100 L 50 50 1 1 B
X GND 4 0 -400 100 U 50 50 1 1 W
X Shield 5 -100 -400 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_USB_B_Micro
#
DEF Connector_USB_B_Micro J 0 40 Y Y 1 F N
F0 "J" -200 450 50 H V L CNN
F1 "Connector_USB_B_Micro" -200 350 50 H V L CNN
F2 "" 150 -50 50 H I C CNN
F3 "" 150 -50 50 H I C CNN
ALIAS USB_B_Mini
$FPLIST
USB*
$ENDFPLIST
DRAW
C -150 85 25 0 1 10 F
C -25 135 15 0 1 10 F
S -200 -300 200 300 0 1 10 f
S -5 -300 5 -270 0 1 0 N
S 10 50 -20 20 0 1 10 F
S 200 -205 170 -195 0 1 0 N
S 200 -105 170 -95 0 1 0 N
S 200 -5 170 5 0 1 0 N
S 200 195 170 205 0 1 0 N
P 2 0 1 10 -75 85 25 85 N
P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N
P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N
P 4 0 1 10 25 110 25 60 75 85 25 110 F
P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F
P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N
X VBUS 1 300 200 100 L 50 50 1 1 w
X D- 2 300 -100 100 L 50 50 1 1 B
X D+ 3 300 0 100 L 50 50 1 1 B
X ID 4 300 -200 100 L 50 50 1 1 P
X GND 5 0 -400 100 U 50 50 1 1 w
X Shield 6 -100 -400 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Crystal
#
DEF Device_Crystal Y 0 40 N N 1 F N
F0 "Y" 0 150 50 H V C CNN
F1 "Device_Crystal" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Crystal*
$ENDFPLIST
DRAW
S -45 100 45 -100 0 1 12 N
P 2 0 1 0 -100 0 -75 0 N
P 2 0 1 20 -75 -50 -75 50 N
P 2 0 1 20 75 -50 75 50 N
P 2 0 1 0 100 0 75 0 N
X 1 1 -150 0 50 R 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 10 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# MCU_Microchip_ATmega_ATmega32U4-AU
#
DEF MCU_Microchip_ATmega_ATmega32U4-AU U 0 20 Y Y 1 F N
F0 "U" -500 1750 50 H V L BNN
F1 "MCU_Microchip_ATmega_ATmega32U4-AU" 100 -1750 50 H V L TNN
F2 "Package_QFP:TQFP-44_10x10mm_P0.8mm" 0 0 50 H I C CIN
F3 "" 0 0 50 H I C CNN
ALIAS ATmega16U4RC-AU ATmega32U4-AU ATmega32U4RC-AU
$FPLIST
TQFP*10x10mm*P0.8mm*
$ENDFPLIST
DRAW
S -500 -1700 500 1700 0 1 10 f
X PE6 1 600 -700 100 L 50 50 1 1 B
X PB2 10 600 1300 100 L 50 50 1 1 B
X PB3 11 600 1200 100 L 50 50 1 1 B
X PB7 12 600 800 100 L 50 50 1 1 B
X ~RESET 13 -600 1500 100 R 50 50 1 1 I
X VCC 14 0 1800 100 D 50 50 1 1 W
X GND 15 0 -1800 100 U 50 50 1 1 W
X XTAL2 16 -600 1100 100 R 50 50 1 1 O
X XTAL1 17 -600 1300 100 R 50 50 1 1 I
X PD0 18 600 300 100 L 50 50 1 1 B
X PD1 19 600 200 100 L 50 50 1 1 B
X UVCC 2 -100 1800 100 D 50 50 1 1 W
X PD2 20 600 100 100 L 50 50 1 1 B
X PD3 21 600 0 100 L 50 50 1 1 B
X PD5 22 600 -200 100 L 50 50 1 1 B
X GND 23 0 -1800 100 U 50 50 1 1 P N
X AVCC 24 100 1800 100 D 50 50 1 1 W
X PD4 25 600 -100 100 L 50 50 1 1 B
X PD6 26 600 -300 100 L 50 50 1 1 B
X PD7 27 600 -400 100 L 50 50 1 1 B
X PB4 28 600 1100 100 L 50 50 1 1 B
X PB5 29 600 1000 100 L 50 50 1 1 B
X D- 3 -600 400 100 R 50 50 1 1 B
X PB6 30 600 900 100 L 50 50 1 1 B
X PC6 31 600 600 100 L 50 50 1 1 B
X PC7 32 600 500 100 L 50 50 1 1 B
X ~HWB~/PE2 33 600 -600 100 L 50 50 1 1 B
X VCC 34 0 1800 100 D 50 50 1 1 P N
X GND 35 0 -1800 100 U 50 50 1 1 P N
X PF7 36 600 -1400 100 L 50 50 1 1 B
X PF6 37 600 -1300 100 L 50 50 1 1 B
X PF5 38 600 -1200 100 L 50 50 1 1 B
X PF4 39 600 -1100 100 L 50 50 1 1 B
X D+ 4 -600 500 100 R 50 50 1 1 B
X PF1 40 600 -1000 100 L 50 50 1 1 B
X PF0 41 600 -900 100 L 50 50 1 1 B
X AREF 42 -600 900 100 R 50 50 1 1 P
X GND 43 0 -1800 100 U 50 50 1 1 P N
X AVCC 44 100 1800 100 D 50 50 1 1 P N
X UGND 5 -100 -1800 100 U 50 50 1 1 P
X UCAP 6 -600 200 100 R 50 50 1 1 P
X VBUS 7 -600 700 100 R 50 50 1 1 I
X PB0 8 600 1500 100 L 50 50 1 1 B
X PB1 9 600 1400 100 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# Memory_Controller_CH376S
#
DEF Memory_Controller_CH376S U 0 40 Y Y 1 F N
F0 "U" -450 950 50 H V L CNN
F1 "Memory_Controller_CH376S" 250 950 50 H V L CNN
F2 "Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm" 0 -1350 50 H I C CIN
F3 "" 0 250 50 H I C CNN
$FPLIST
SSOP*5.3x7.2mm*P0.65mm*
$ENDFPLIST
DRAW
S -450 900 450 -900 0 1 0 f
X ~INT~ 1 -600 750 150 R 50 50 1 1 O
X UD+ 10 600 750 150 L 50 50 1 1 B
X UD- 11 600 650 150 L 50 50 1 1 B
X GND 12 0 -1050 150 U 50 50 1 1 W
X XI 13 -600 450 150 R 50 50 1 1 I
X XO 14 -600 350 150 R 50 50 1 1 O
X D0 15 600 -50 150 L 50 50 1 1 T
X D1 16 600 -150 150 L 50 50 1 1 T
X D2 17 600 -250 150 L 50 50 1 1 T
X SCS/D3 18 600 -350 150 L 50 50 1 1 T
X BZ/D4 19 600 -450 150 L 50 50 1 1 T
X RSTI 2 -600 650 150 R 50 50 1 1 I
X SCK/D5 20 600 -550 150 L 50 50 1 1 T
X SDI/D6 21 600 -650 150 L 50 50 1 1 T
X SDO/D7 22 600 -750 150 L 50 50 1 1 T
X SD_CS 23 600 150 150 L 50 50 1 1 C
X ~ACT 24 -600 150 150 R 50 50 1 1 C
X SD_DO 25 600 350 150 L 50 50 1 1 O
X SD_CK 26 600 250 150 L 50 50 1 1 O
X ~PCS 27 -600 -750 150 R 50 50 1 1 I
X VCC 28 -100 1050 150 D 50 50 1 1 W
X ~WR 3 -600 -550 150 R 50 50 1 1 I
X ~RD 4 -600 -450 150 R 50 50 1 1 I
X TXD 5 -600 -50 150 R 50 50 1 1 B
X RXD 6 -600 -150 150 R 50 50 1 1 I
X SD_DI 7 600 450 150 L 50 50 1 1 I
X A0 8 -600 -350 150 R 50 50 1 1 I
X V3 9 100 1050 150 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Memory_Flash_29F016-TSOP-SP
#
DEF Memory_Flash_29F016-TSOP-SP U 0 20 Y Y 1 F N
F0 "U" 100 1350 50 H V C CNN
F1 "Memory_Flash_29F016-TSOP-SP" 500 -1050 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -350 1250 350 -950 0 1 0 f
X A12 10 -600 -50 250 R 50 50 1 1 I
X ~CE 11 600 250 250 L 50 50 1 1 I I
X VCC 12 -50 1550 300 D 50 50 1 1 I
X ~RESET 14 600 -200 250 L 50 50 1 1 I I
X A11 15 -600 50 250 R 50 50 1 1 I
X A10 16 -600 150 250 R 50 50 1 1 I
X A9 17 -600 250 250 R 50 50 1 1 I
X A8 18 -600 350 250 R 50 50 1 1 I
X A7 19 -600 450 250 R 50 50 1 1 I
X A6 20 -600 550 250 R 50 50 1 1 I
X A5 21 -600 650 250 R 50 50 1 1 I
X A4 22 -600 750 250 R 50 50 1 1 I
X A3 27 -600 850 250 R 50 50 1 1 I
X A2 28 -600 950 250 R 50 50 1 1 I
X A1 29 -600 1050 250 R 50 50 1 1 I
X A19 3 -600 -750 250 R 50 50 1 1 I
X A0 30 -600 1150 250 R 50 50 1 1 I
X D0 31 600 1150 250 L 50 50 1 1 T
X D1 32 600 1050 250 L 50 50 1 1 T
X D2 33 600 950 250 L 50 50 1 1 T
X D3 34 600 850 250 L 50 50 1 1 T
X GND 35 -50 -1250 300 U 50 50 1 1 I
X GND 36 50 -1250 300 U 50 50 1 1 I
X VCC 37 50 1550 300 D 50 50 1 1 I
X D4 38 600 750 250 L 50 50 1 1 T
X D5 39 600 650 250 L 50 50 1 1 T
X A18 4 -600 -650 250 R 50 50 1 1 I
X D6 40 600 550 250 L 50 50 1 1 T
X D7 41 600 450 250 L 50 50 1 1 T
X RY/~BY 42 600 -50 250 L 50 50 1 1 I
X ~OE 43 600 150 250 L 50 50 1 1 I I
X ~WE 44 600 50 250 L 50 50 1 1 I I
X A20 46 -600 -850 250 R 50 50 1 1 I
X A17 5 -600 -550 250 R 50 50 1 1 I
X A16 6 -600 -450 250 R 50 50 1 1 I
X A15 7 -600 -350 250 R 50 50 1 1 I
X A14 8 -600 -250 250 R 50 50 1 1 I
X A13 9 -600 -150 250 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# PCMCIA_PCMCIA
#
DEF PCMCIA_PCMCIA C 0 40 Y Y 1 F N
F0 "C" -250 2400 50 H V C CNN
F1 "PCMCIA_PCMCIA" 0 -2100 50 H V C CNN
F2 "" 1200 -1300 50 H I C CNN
F3 "" 1200 -1300 50 H I C CNN
DRAW
S 400 -2050 -400 2350 0 1 0 f
X GND 1 -600 -1600 197 R 50 50 1 1 W
X A11 10 600 -450 197 L 50 50 1 1 I
X A9 11 600 -350 197 L 50 50 1 1 I
X A8 12 600 -250 197 L 50 50 1 1 I
X A13 13 600 -750 197 L 50 50 1 1 I
X A14 14 600 -850 197 L 50 50 1 1 I
X ~WE 15 -600 -150 197 R 50 50 1 1 I
X READY/~IRQ 16 -600 -400 197 R 50 50 1 1 O
X VCC 17 -600 2200 197 R 50 50 1 1 W
X VPP1 18 -600 1900 197 R 50 50 1 1 W
X A16 19 600 -1050 197 L 50 50 1 1 I
X D3 2 600 1900 197 L 50 50 1 1 B
X A15 20 600 -950 197 L 50 50 1 1 I
X A12 21 600 -650 197 L 50 50 1 1 I
X A7 22 600 -150 197 L 50 50 1 1 I
X A6 23 600 -50 197 L 50 50 1 1 I
X A5 24 600 50 197 L 50 50 1 1 I
X A4 25 600 150 197 L 50 50 1 1 I
X A3 26 600 250 197 L 50 50 1 1 I
X A2 27 600 350 197 L 50 50 1 1 I
X A1 28 600 450 197 L 50 50 1 1 I
X A0 29 600 550 197 L 50 50 1 1 I
X D4 3 600 1800 197 L 50 50 1 1 B
X D0 30 600 2200 197 L 50 50 1 1 B
X D1 31 600 2100 197 L 50 50 1 1 B
X D2 32 600 2000 197 L 50 50 1 1 B
X WP/~IOIS16 33 -600 -500 197 R 50 50 1 1 O
X GND 34 -600 -1700 197 R 50 50 1 1 W
X GND 35 -600 -1800 197 R 50 50 1 1 W
X ~CD1 36 -600 750 197 R 50 50 1 1 O
X D11 37 600 1100 197 L 50 50 1 1 B
X D12 38 600 1000 197 L 50 50 1 1 B
X D5 4 600 1700 197 L 50 50 1 1 B
X D14 40 600 800 197 L 50 50 1 1 B
X D15 41 600 700 197 L 50 50 1 1 B
X ~CE2 42 -600 300 197 R 50 50 1 1 I
X ~VS1 43 -600 1250 197 R 50 50 1 1 I
X ~IORD 44 -600 -700 197 R 50 50 1 1 I
X ~IOWR 45 -600 -800 197 R 50 50 1 1 I
X A17 46 600 -1150 197 L 50 50 1 1 I
X A18 47 600 -1250 197 L 50 50 1 1 I
X A19 48 600 -1350 197 L 50 50 1 1 I
X A20 49 600 -1450 197 L 50 50 1 1 I
X D6 5 600 1600 197 L 50 50 1 1 B
X A21 50 600 -1550 197 L 50 50 1 1 I
X VCC 51 -600 2100 197 R 50 50 1 1 W
X VPP2 52 -600 1800 197 R 50 50 1 1 W
X A22 53 600 -1650 197 L 50 50 1 1 I
X A23 54 600 -1750 197 L 50 50 1 1 I
X A24 55 600 -1850 197 L 50 50 1 1 I
X A25 56 600 -1950 197 L 50 50 1 1 I
X ~VS2 57 -600 1150 197 R 50 50 1 1 O
X RESET 58 -600 1550 197 R 50 50 1 1 I
X ~WAIT 59 -600 -300 197 R 50 50 1 1 O
X D7 6 600 1500 197 L 50 50 1 1 B
X ~INPACK 60 -600 -900 197 R 50 50 1 1 O
X SPK/BV2 62 -600 -1300 197 R 50 50 1 1 O
X ~STSCHG~/BV1 63 -600 -1200 197 R 50 50 1 1 O
X D8 64 600 1400 197 L 50 50 1 1 B
X D9 65 600 1300 197 L 50 50 1 1 B
X D10 66 600 1200 197 L 50 50 1 1 B
X ~CD2 67 -600 650 197 R 50 50 1 1 O
X GND 68 -600 -1900 197 R 50 50 1 1 W
X ~CE1 7 -600 400 197 R 50 50 1 1 I
X A10 8 600 -550 197 L 50 50 1 1 I
X D13 9 600 900 197 L 50 50 1 1 B
X ~OE 9 -600 -50 197 R 50 50 1 1 I
X GND G1 -450 -2200 100 R 50 50 1 1 P N
X GND G2 -450 -2300 100 R 50 50 1 1 P N
X GND G3 -450 -2400 100 R 50 50 1 1 P N
X GND G4 -450 -2500 100 R 50 50 1 1 P N
X GND G5 300 -2200 100 R 50 50 1 1 P N
X GND G6 300 -2300 100 R 50 50 1 1 P N
X GND G7 300 -2400 100 R 50 50 1 1 P N
X GND G8 300 -2500 100 R 50 50 1 1 P N
ENDDRAW
ENDDEF
#
# Transistor_BJT_BC847
#
DEF Transistor_BJT_BC847 Q 0 0 Y N 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "Transistor_BJT_BC847" 200 0 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23" 200 -75 50 H I L CIN
F3 "" 0 0 50 H I L CNN
ALIAS BC818 BC846 BC847 BC848 BC849 BC850 MMBT3904 MMBT5550L MMBT5551L
$FPLIST
SOT?23*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X B 1 -200 0 225 R 50 50 1 1 I
X E 2 100 -200 100 U 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_VCC
#
DEF power_VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

Binary file not shown.

View File

@ -0,0 +1,256 @@
update=2022 June 17, Friday 16:00:19
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=./
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.15
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.15
TrackWidth3=0.2
TrackWidth4=0.3
TrackWidth5=0.4
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter2=0.45
ViaDrill2=0.3
ViaDiameter3=0.5
ViaDrill3=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,8 @@
EESchema-DOCLIB Version 2.0
#
$CMP PCMCIA
D PCMCIA Card Socket
K PCMCIA pccard
$ENDCMP
#
#End Doc Library

View File

@ -0,0 +1,8 @@
EESchema-DOCLIB Version 2.0
#
$CMP PCMCIA
D PCMCIA Card Socket
K PCMCIA pccard
$ENDCMP
#
#End Doc Library

View File

@ -0,0 +1,91 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# PCMCIA
#
DEF PCMCIA C 0 40 Y Y 1 F N
F0 "C" -250 2400 50 H V C CNN
F1 "PCMCIA" 0 -2100 50 H V C CNN
F2 "" 1200 -1300 50 H I C CNN
F3 "" 1200 -1300 50 H I C CNN
DRAW
S 400 -2050 -400 2350 0 1 0 f
X GND 1 -600 -1600 197 R 50 50 1 1 W
X A11 10 600 -450 197 L 50 50 1 1 I
X A9 11 600 -350 197 L 50 50 1 1 I
X A8 12 600 -250 197 L 50 50 1 1 I
X A13 13 600 -750 197 L 50 50 1 1 I
X A14 14 600 -850 197 L 50 50 1 1 I
X ~WE 15 -600 -150 197 R 50 50 1 1 I
X READY/~IRQ 16 -600 -400 197 R 50 50 1 1 O
X VCC 17 -600 2200 197 R 50 50 1 1 W
X VPP1 18 -600 1900 197 R 50 50 1 1 W
X A16 19 600 -1050 197 L 50 50 1 1 I
X D3 2 600 1900 197 L 50 50 1 1 B
X A15 20 600 -950 197 L 50 50 1 1 I
X A12 21 600 -650 197 L 50 50 1 1 I
X A7 22 600 -150 197 L 50 50 1 1 I
X A6 23 600 -50 197 L 50 50 1 1 I
X A5 24 600 50 197 L 50 50 1 1 I
X A4 25 600 150 197 L 50 50 1 1 I
X A3 26 600 250 197 L 50 50 1 1 I
X A2 27 600 350 197 L 50 50 1 1 I
X A1 28 600 450 197 L 50 50 1 1 I
X A0 29 600 550 197 L 50 50 1 1 I
X D4 3 600 1800 197 L 50 50 1 1 B
X D0 30 600 2200 197 L 50 50 1 1 B
X D1 31 600 2100 197 L 50 50 1 1 B
X D2 32 600 2000 197 L 50 50 1 1 B
X WP/~IOIS16 33 -600 -500 197 R 50 50 1 1 O
X GND 34 -600 -1700 197 R 50 50 1 1 W
X GND 35 -600 -1800 197 R 50 50 1 1 W
X ~CD1 36 -600 750 197 R 50 50 1 1 O
X D11 37 600 1100 197 L 50 50 1 1 B
X D12 38 600 1000 197 L 50 50 1 1 B
X D5 4 600 1700 197 L 50 50 1 1 B
X D14 40 600 800 197 L 50 50 1 1 B
X D15 41 600 700 197 L 50 50 1 1 B
X ~CE2 42 -600 300 197 R 50 50 1 1 I
X ~VS1 43 -600 1250 197 R 50 50 1 1 I
X ~IORD 44 -600 -700 197 R 50 50 1 1 I
X ~IOWR 45 -600 -800 197 R 50 50 1 1 I
X A17 46 600 -1150 197 L 50 50 1 1 I
X A18 47 600 -1250 197 L 50 50 1 1 I
X A19 48 600 -1350 197 L 50 50 1 1 I
X A20 49 600 -1450 197 L 50 50 1 1 I
X D6 5 600 1600 197 L 50 50 1 1 B
X A21 50 600 -1550 197 L 50 50 1 1 I
X VCC 51 -600 2100 197 R 50 50 1 1 W
X VPP2 52 -600 1800 197 R 50 50 1 1 W
X A22 53 600 -1650 197 L 50 50 1 1 I
X A23 54 600 -1750 197 L 50 50 1 1 I
X A24 55 600 -1850 197 L 50 50 1 1 I
X A25 56 600 -1950 197 L 50 50 1 1 I
X ~VS2 57 -600 1150 197 R 50 50 1 1 O
X RESET 58 -600 1550 197 R 50 50 1 1 I
X ~WAIT 59 -600 -300 197 R 50 50 1 1 O
X D7 6 600 1500 197 L 50 50 1 1 B
X ~INPACK 60 -600 -900 197 R 50 50 1 1 O
X SPK/BV2 62 -600 -1300 197 R 50 50 1 1 O
X ~STSCHG~/BV1 63 -600 -1200 197 R 50 50 1 1 O
X D8 64 600 1400 197 L 50 50 1 1 B
X D9 65 600 1300 197 L 50 50 1 1 B
X D10 66 600 1200 197 L 50 50 1 1 B
X ~CD2 67 -600 650 197 R 50 50 1 1 O
X GND 68 -600 -1900 197 R 50 50 1 1 W
X ~CE1 7 -600 400 197 R 50 50 1 1 I
X A10 8 600 -550 197 L 50 50 1 1 I
X D13 9 600 900 197 L 50 50 1 1 B
X ~OE 9 -600 -50 197 R 50 50 1 1 I
X GND G1 -450 -2200 100 R 50 50 1 1 P N
X GND G2 -450 -2300 100 R 50 50 1 1 P N
X GND G3 -450 -2400 100 R 50 50 1 1 P N
X GND G4 -450 -2500 100 R 50 50 1 1 P N
X GND G5 300 -2200 100 R 50 50 1 1 P N
X GND G6 300 -2300 100 R 50 50 1 1 P N
X GND G7 300 -2400 100 R 50 50 1 1 P N
X GND G8 300 -2500 100 R 50 50 1 1 P N
ENDDRAW
ENDDEF
#
#End Library

View File

@ -0,0 +1,86 @@
(module PCMCIA-Female (layer F.Cu) (tedit 62AC6509)
(fp_text reference REF** (at 0 2.2225) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PCMCIA-Female (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -22.225 2.2225) (end -21.2725 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -21.9075 2.2225) (end -22.225 2.2225) (layer F.SilkS) (width 0.12))
(fp_line (start -20.32 2.2225) (end -21.9075 2.2225) (layer F.SilkS) (width 0.12))
(fp_line (start -21.2725 1.27) (end -20.32 2.2225) (layer F.SilkS) (width 0.12))
(fp_text user 1 (at -21.2725 3.175) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 68 (at 21.2725 3.175) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd rect (at -21.2725 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -20.6375 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at -20.0025 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -19.3675 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at -18.7325 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at -18.0975 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at -17.4625 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at -16.8275 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at -16.1925 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at -15.5575 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at -14.9225 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at -14.2875 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at -13.6525 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at -13.0175 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at -12.3825 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 16 smd rect (at -11.7475 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 17 smd rect (at -11.1125 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 18 smd rect (at -10.4775 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 19 smd rect (at -9.8425 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 20 smd rect (at -9.2075 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at -8.5725 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 22 smd rect (at -7.9375 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 23 smd rect (at -7.3025 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 24 smd rect (at -6.6675 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 25 smd rect (at -6.0325 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 26 smd rect (at -5.3975 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 27 smd rect (at -4.7625 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 28 smd rect (at -4.1275 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 29 smd rect (at -3.4925 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 30 smd rect (at -2.8575 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 31 smd rect (at -2.2225 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 32 smd rect (at -1.5875 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at -0.9525 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 34 smd rect (at -0.3175 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 35 smd rect (at 0.3175 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 36 smd rect (at 0.9525 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 37 smd rect (at 1.5875 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 38 smd rect (at 2.2225 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 39 smd rect (at 2.8575 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 40 smd rect (at 3.4925 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 41 smd rect (at 4.1275 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 42 smd rect (at 4.7625 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 43 smd rect (at 5.3975 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 44 smd rect (at 6.0325 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 45 smd rect (at 6.6675 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 46 smd rect (at 7.3025 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 47 smd rect (at 7.9375 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 48 smd rect (at 8.5725 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 49 smd rect (at 9.2075 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 50 smd rect (at 9.8425 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 51 smd rect (at 10.4775 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 52 smd rect (at 11.1125 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 53 smd rect (at 11.7475 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 54 smd rect (at 12.3825 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 55 smd rect (at 13.0175 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 56 smd rect (at 13.6525 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 57 smd rect (at 14.2875 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 58 smd rect (at 14.9225 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 59 smd rect (at 15.5575 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 60 smd rect (at 16.1925 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 61 smd rect (at 16.8275 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 62 smd rect (at 17.4625 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 63 smd rect (at 18.0975 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 64 smd rect (at 18.7325 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 65 smd rect (at 19.3675 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 66 smd rect (at 20.0025 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 67 smd rect (at 20.6375 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 68 smd rect (at 21.2725 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
)

View File

@ -0,0 +1,94 @@
(module PCMCIA-Sheilded-Female (layer F.Cu) (tedit 62AC8D3C)
(fp_text reference REF** (at 0 2.2225) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PCMCIA-Sheilded-Female (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -22.225 2.2225) (end -21.2725 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -21.9075 2.2225) (end -22.225 2.2225) (layer F.SilkS) (width 0.12))
(fp_line (start -20.32 2.2225) (end -21.9075 2.2225) (layer F.SilkS) (width 0.12))
(fp_line (start -21.2725 1.27) (end -20.32 2.2225) (layer F.SilkS) (width 0.12))
(fp_text user 1 (at -21.2725 3.175) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 68 (at 21.2725 3.175) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd rect (at -21.2725 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad G1 smd rect (at -19.05 2.2225) (size 1 1.5) (layers F.Cu F.Paste F.Mask))
(pad G2 smd rect (at -13.97 2.2225) (size 1 1.5) (layers F.Cu F.Paste F.Mask))
(pad G3 smd rect (at -8.89 2.2225) (size 1 1.5) (layers F.Cu F.Paste F.Mask))
(pad G4 smd rect (at -3.81 2.2225) (size 1 1.5) (layers F.Cu F.Paste F.Mask))
(pad G8 smd rect (at 19.05 2.2225) (size 1 1.5) (layers F.Cu F.Paste F.Mask))
(pad G7 smd rect (at 13.97 2.2225) (size 1 1.5) (layers F.Cu F.Paste F.Mask))
(pad G6 smd rect (at 8.89 2.2225) (size 1 1.5) (layers F.Cu F.Paste F.Mask))
(pad G5 smd rect (at 3.81 2.2225) (size 1 1.5) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -20.6375 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at -20.0025 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -19.3675 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at -18.7325 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at -18.0975 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at -17.4625 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at -16.8275 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at -16.1925 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at -15.5575 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at -14.9225 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at -14.2875 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at -13.6525 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at -13.0175 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at -12.3825 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 16 smd rect (at -11.7475 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 17 smd rect (at -11.1125 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 18 smd rect (at -10.4775 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 19 smd rect (at -9.8425 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 20 smd rect (at -9.2075 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at -8.5725 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 22 smd rect (at -7.9375 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 23 smd rect (at -7.3025 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 24 smd rect (at -6.6675 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 25 smd rect (at -6.0325 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 26 smd rect (at -5.3975 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 27 smd rect (at -4.7625 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 28 smd rect (at -4.1275 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 29 smd rect (at -3.4925 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 30 smd rect (at -2.8575 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 31 smd rect (at -2.2225 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 32 smd rect (at -1.5875 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at -0.9525 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 34 smd rect (at -0.3175 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 35 smd rect (at 0.3175 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 36 smd rect (at 0.9525 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 37 smd rect (at 1.5875 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 38 smd rect (at 2.2225 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 39 smd rect (at 2.8575 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 40 smd rect (at 3.4925 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 41 smd rect (at 4.1275 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 42 smd rect (at 4.7625 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 43 smd rect (at 5.3975 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 44 smd rect (at 6.0325 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 45 smd rect (at 6.6675 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 46 smd rect (at 7.3025 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 47 smd rect (at 7.9375 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 48 smd rect (at 8.5725 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 49 smd rect (at 9.2075 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 50 smd rect (at 9.8425 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 51 smd rect (at 10.4775 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 52 smd rect (at 11.1125 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 53 smd rect (at 11.7475 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 54 smd rect (at 12.3825 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 55 smd rect (at 13.0175 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 56 smd rect (at 13.6525 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 57 smd rect (at 14.2875 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 58 smd rect (at 14.9225 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 59 smd rect (at 15.5575 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 60 smd rect (at 16.1925 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 61 smd rect (at 16.8275 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 62 smd rect (at 17.4625 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 63 smd rect (at 18.0975 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 64 smd rect (at 18.7325 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 65 smd rect (at 19.3675 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 66 smd rect (at 20.0025 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 67 smd rect (at 20.6375 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
(pad 68 smd rect (at 21.2725 0) (size 0.4 1.5) (layers F.Cu F.Paste F.Mask))
)

View File

@ -0,0 +1,15 @@
3310940742429
PCMCIA
PCMCIA-Female
0
68
68
PCMCIA
PCMCIA-Sheilded-Female
0
76
76

View File

@ -0,0 +1,3 @@
(fp_lib_table
(lib (name PCMCIA)(type KiCad)(uri ${KIPRJMOD}/PCMCIA.pretty)(options "")(descr ""))
)

View File

@ -0,0 +1,3 @@
(sym_lib_table
(lib (name PCMCIA)(type Legacy)(uri ${KIPRJMOD}/PCMCIA.lib)(options "")(descr ""))
)

BIN
Images/Board Overview.png Normal file

Binary file not shown.

After

Width:  |  Height:  |  Size: 3.8 MiB

BIN
Images/Watchdog.png Normal file

Binary file not shown.

After

Width:  |  Height:  |  Size: 159 KiB

Some files were not shown because too many files have changed in this diff Show More